These shift registers are very easy and fast to utilize.The advantages of the PIPO shift register include the following. One CLK pulse is enough to load and one CLK pulse is to unload to the temporary storage device. Here, the data which is given is in a parallel format to the parallel i/p pins like DA to D0 and after that shifted to the equivalent o/p pins from QA to QD once the shift registers are clocked. This register is simply utilized like a temporary storage device similar to the SISO Shift register, so it works like a delay element. For each FF, the data is provided as i/p and the o/p is received from every FF individually. In this kind of shift register, there is no interconnection between the individual FFs because no serial data shifting is necessary. In this circuit, both the CLR and CLK signals are connected to 4 D FFs. This logic circuit is designed with 4 D-FFs which is shown in the diagram. The input allowed by this type of shift register is parallel & gives a parallel output. The circuit diagram of the PIPO shift register is shown below.
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